Advanced packaging materials: what holds AI chips together

Advanced packaging materials are the polymer films, adhesives, molding compounds, and composites that insulate, bond, and cool chips stacked in 2.5D and 3D packages. A short list of families survives the screen, because each layer must hold its dimensions and its interfaces through three reflow cycles at 260 degrees Celsius, then prove it over 18 to 24 months of reliability data. In 2026 these materials became a product definition problem, not a purchasing detail.

Why Packaging Got Repriced in 2026

Packaging used to be logistics: put the die in a shell, bring out the pins, pass the reliability tests, and keep the cost down. In 2026 that framing broke. Three numbers explain why.

Industry trackers put the 2026 packaging test and assembly market at about 96 billion US dollars, of which advanced packaging accounts for roughly 52 billion, or 54%, crossing the halfway mark for the first time. CoWoS and its associated test content now carry 21% to 25% of the cost of a high-end compute chip, close to the value of leading-edge wafer fabrication. And gross margins in advanced packaging run at 48% to 55%, the thickest slice of the chain.

Capacity shows the same pressure. TSMC’s CoWoS capacity went from about 35,000 wafers per month in 2024 to a planned 120,000 to 140,000 by the end of 2026, and ASE plus other OSAT partners add another 50,000 to 60,000, putting the industry near 200,000 per month. Demand ran at about 370,000 wafers per year in 2024, 670,000 to 690,000 in 2025, and is expected to pass 1 million in 2026, with 2027 possibly above 2.5 million. Even after capacity nearly tripled in two years, TSMC still fills only about 80% of orders from its biggest customers.

For advanced packaging materials the quieter shift is where the difficulty now sits. Equipment can be bought and lines can be built. How much a package warps in reflow, whether an underfill flows into a 50 micron gap, and whether a substrate stays flat after three cycles at 260 C are decided by formulation, and formulation cannot be purchased.

Six Gates: How Advanced Packaging Materials Get Screened

Advanced packaging is a broad label. Split its demands into six measurable gates and the comparisons that follow have a common language.

The first five gates are engineering problems that money can solve. The sixth is a clock problem. A supplier can hand over samples that hit every number and still sit outside a qualified vendor list for two years, because the customer has to rebuild the whole reliability set: temperature cycling, biased humidity, drop, and board-level tests. Swapping one substrate material triggers 18 to 24 months of that work, and if the new material fails mid-stream the loss is counted in batches. In this industry expensive is survivable and uncertain is not.

Nine Layers, Seven Polymers: Anatomy of a Flip-Chip Package

Slice an FC-BGA package vertically and the material sequence reads: lid, thermal interface material, die, microbumps with underfill, redistribution layer, build-up dielectric, core, solder ball, motherboard. Seven of the nine are polymers or polymer composites.

The failure-prone part is not any single layer. Failures rarely look like a material breaking; they look like two materials separating, because their coefficients of thermal expansion differ and every temperature swing pulls them apart. The interface, not the layer, is the weak point, which is why adhesion and CTE matching get screened before bulk properties.

The Survivors: What Each Advanced Packaging Material Does

The screen is harsh: survive 260 C, carry no migratable ions, and still be patternable at 2 microns or filmable at 20 microns. Seven families of advanced packaging materials make the cut, and they share one trait. They are not the strongest materials available but the most controllable ones.

PEEK withstands far higher temperatures than epoxy, yet in packaging it is confined to CMP retainer rings: it cannot be photopatterned, cannot be made into thin films, and its dielectric properties miss the bar. Epoxy, mediocre on paper, is the highest-volume packaging material because its process window is wide, its batches are stable, and its supply chain is mature. The first principle of selection here is repeatability, not performance. Within one lot of 1,000 wafers the dielectric thickness must match from the first wafer to the last at nanometer scale, and batch 20 must cure on the same process curve as batch 1. That is harder than hitting one impressive number.

Heat, Moisture, and Warpage: Surviving 260 Degrees Celsius Three Times

Lead-free assembly pushed the reflow peak from 235 C to 245 to 260 C, and a chip sees that peak at least three times: once for double-sided mounting, once for rework, and once in the customer’s second reflow.

Moisture is the sharper threat. Molding compounds and dielectric layers typically absorb 0.1% to 0.5% water, harmless at room temperature. Inside a 260 C reflow oven that water vaporizes within seconds and expands roughly a thousandfold, building steam pressure until it exceeds interfacial adhesion and the package bulges like popcorn. The industry manages this through JEDEC moisture sensitivity levels: MSL 1 parts tolerate unlimited floor exposure, while MSL 3 parts must be baked after 168 hours. Larger packages with more layers trap more interfaces and give the steam fewer escape paths, so the problem grows with package size.

Warpage is the other scaling wall. Warpage grows with the square of package size, so moving from 50 by 50 mm to beyond 100 by 100 mm turns a manageable deflection into a defect source, and a 510 by 515 mm panel with poor CTE control can warp by millimeters at the edge, enough to break exposure alignment. That is the case for glass substrates: glass can be tuned to 3 to 5 ppm/C, close to silicon at 2.6, while organic cores sit at 10 to 17. In large-panel trials glass cut warpage by more than half compared with organic substrates. The trade is rigidity for flatness, paid for in brittleness and processing difficulty.

Photosensitive Polyimide: The Polymer That Behaves Like Photoresist

Photosensitive polyimide, shortened to PSPI, is the core material for redistribution layers and TSV insulation. Its advantage is that it is both the dielectric layer and the photo-defined pattern: exposing and developing it directly removes the coating, lithography, etch, and strip steps, four operations that used to sit between deposition and the next layer.

The cost is a formulation squeezed from five directions at once. One system must deliver photosensitivity, imidization temperature, CTE, dielectric constant, and adhesion to copper, and those five pull against each other.

The temperature column is the whole story. Traditional PSPI imidizes at 350 to 400 C, fine for front-end work and fatal in packaging, where the die stack is already assembled and 400 C would remelt the solder. Low-temperature PSPI cured at 200 to 250 C is therefore the entry point domestic suppliers are aiming at, and their first real opening in the category.

In 2026 the picture splits: mature categories in volume supply, advanced grades still in validation. Ruilian New Materials ships PSPI monomers in volume to Japanese leaders and reported 74% year-on-year growth in packaging adhesive monomer sales. Aisen has taken orders for low-temperature PSPI from leading customers, the first zero-to-one step for the domestic category. Dinglong already ships non-photosensitive and photosensitive polyimide into G8.6 AMOLED lines, with 236 million yuan of display material revenue in the first half of 2026. The most aggressive claim comes from Bomi Technology, which has passed device-level validation with claimed 0.1 micron resolution and Dk below 3.0, figures the market treats as optimistic until customers confirm them.

The bottleneck is not the formula. High-end PSPI supply is expected to stay tight through 2028 for three unglamorous reasons: memory customers take two to three years to qualify, advanced packaging PSPI is bound to a customer’s specific RDL process window so a material swap means re-tuning an entire process curve, and batch consistency only accumulates with time. 2026 delivered the zero-to-one step; 2027 and 2028 are the one-to-ten phase.

ABF Film: One Supplier, Thirty Years, and a 30 Percent Cut

ABF film is the most complete single-supplier monopoly in advanced packaging materials. The resin was found by accident in the 1970s in a by-product of monosodium glutamate production at Ajinomoto. Intel first adopted it in 1996, volume production followed in 1999, and for roughly thirty years patent walls, process know-how, and binding to the largest customers have held the category: global share of 90% to 95% with margins above 50%.

AI demand tightened the knot. A traditional PC substrate needs 4 to 6 ABF layers, a high-end AI package needs 8 to 16, and the newest platforms reach 20 to 24, so a single AI chip consumes 5 to 10 times the ABF film of a conventional one. The substrate area for one leading GPU platform is 123% larger than the previous generation.

In early August 2026 Ajinomoto told customers in mainland China that it would cut their allocation by 30%. The significance is not the price. In a market already running full with 12 to 14 month lead times, it proved the supplier can practice selective allocation. Substrate lead times had already stretched from 6 to 8 months in early 2025 to 12 to 14 months, all six major suppliers’ 2026 capacity was booked, and second-tier suppliers began auctioning residual capacity, the clearest signal of extreme imbalance.

What is scarce is not film but film that passes AI substrate validation. The specification sheet is unforgiving: surface roughness Ra below 100 nm, Dk at or below 3.0 and Df at or below 0.008 at 1 GHz, CTE at or below 12 ppm/C, peel strength to electroless copper of 196 to 785 N/m, and dielectric constant uniformity within 5%. Miss any one and 6/6 micron or even 2/2 micron lines cannot be built.

Three domestic routes are running in parallel: ABF-like modified epoxy, with CBF film from Huazheng New Materials and NBF from Newfes; extension by established laminate producers such as Shengyi Technology and Nanya New Material, now in small-volume trial production; and cross-industry acquisition, with Lianhua Holdings, a monosodium glutamate company, paying 103 million yuan in April 2026 for an ABF startup whose annual revenue was 6.5 million yuan. The honest scorecard: mainland China’s ABF film self-sufficiency is below 5% against domestic ABF substrate material demand above 12 billion yuan. The incumbent’s replacement plant starts construction in 2028 and produces in 2032, so this is a multi-year constraint, not a quarterly one.

Epoxy Molding Compounds: From Encapsulation to Filling

The role of the molding compound changed. It is no longer just a shell around the die; in stacked packages it is a structural layer between dies. HBM stacks 8, 12, or more DRAM layers with gaps of only tens of microns, too narrow for traditional pre-molded encapsulation, so two new forms appeared: GMC, a granular compound for wafer-level and panel-level compression molding, and MUF, molded underfill that fills and encapsulates in one pass. The more layers HBM stacks, the more MUF’s advantage grows.

Set that against the tonnage: mainland China’s EMC capacity exceeds 140,000 tons per year, about 35% of the world and the largest production base anywhere, with 2025 output of 248,400 tons and a market of 12.84 billion yuan. Between tonnage and share sits a gap: overall localization is about 30%, and in high-end grades only 18% to 22%, while traditional packaging EMC is above 65% domestic. Domestic suppliers can win the mid and low end first because overseas players are raising prices and their new capacity is late, with the Suzhou addition coming online at the end of 2028. The high-end barrier sits in three places: filler surface treatment, resin system formulation, and batch stability. None of those can be bought with equipment.

Underfill and Thermal Interface Materials: The Invisible Load Bearers

An underfill adhesive does one job: it takes the shear stress that CTE mismatch would otherwise dump onto solder joints and carries it in a rigid support layer. It wicks into the gap between die and substrate by capillary action, then cures. The formulation has to satisfy three conflicting demands at once: flow into the gap and fill it completely, lower the CTE without becoming brittle, and cure fast without shrinking much.

China’s underfill market is about 8.5 billion yuan in 2026, more than 90% imported, with localization near 12%. Henkel, Namics, and Hysol dominate, which makes underfill one of the least localized categories in packaging.

A thermal interface material sits between die and lid. As AI chip power moved from 700 W to 2300 W, TIM stopped being an accessory and became a performance limit: at 2300 W silicone grease is no longer enough, and the industry is migrating toward phase-change materials and metal-based compounds.

Temporary Bonding Adhesives: Crutches for 30-Micron Wafers

3D stacking wants wafers as thin as possible. HBM DRAM layers are already ground to 30 to 40 microns, at which point a wafer behaves like plastic wrap: it cannot hold itself and cannot be handled by equipment. A temporary bonding adhesive glues it to a carrier for processing, then releases it intact.

Release is the hard part. Intact means no residue, no stress damage, and no fragments, and the release method decides yield. Laser debonding took 53.2% of the market in 2025. The process chain is short and unforgiving: coat with micron-level total thickness variation, bond without bubbles, thin and process at up to 350 C, laser release at low stress, then clean to sub-nanometer residue.

The absolute market is small, about 123 million US dollars globally in 2025 rising to 348 million by 2032, but prices run 800 to 3,500 US dollars per kilogram with gross margins of 40% to 60% and very high entry barriers. It is a classic small-market, high-stickiness business.

Domestic progress: Phicai Materials, which counts CXMT for 13% to 15% of its revenue, supplies HBM temporary bonding adhesive in volume, and its CoWoS-grade product has entered a second-source sequence at TSMC; Huitian New Materials has passed full-process validation at TongFu and JCET for HBM high-temperature grades, with small-volume supply; Kangda New Materials has passed wafer-level validation at JCET. One boundary matters here: reports of stable volume supply into that foundry’s CoWoS line are market rumor. Public information confirms validation and second-source status only, not stable volume supply. The distance between progress and revenue is where this industry is most often overvalued.

Three Substrate Generations: BT Resin, ABF, and Glass

The substrate translates the chip’s 2 micron lines into the board’s 100 micron lines, and each generation solves the same problem, flatness and CTE, with a different material.

BT resin deserves its own paragraph. Its moisture uptake is 0.2% to 0.5% against 1.0% to 1.5% for polyimide laminates, and its Tg exceeds 200 C versus 135 to 180 C for high-Tg FR-4. BT and ABF are complements, not substitutes: BT supplies the rigid, flat core, and ABF builds the fine lines on top.

A glass substrate trades brittleness for rigidity. With CTE tunable to 3 to 5 ppm/C against silicon’s 2.6, a closer match means less warpage, finer lines, and more layers, and 510 by 515 mm trials showed more than 50% less warpage than organic substrates. The domestic chain moved faster than expected in 2026: BOE achieved fully automated pilot-line throughput with a design capacity of 1,000 substrates per month and has sampled 20-layer large glass substrates to leading compute customers; WoGe produces through-glass vias down to 3 microns with a 150:1 aspect ratio and has entered small-volume supply on a 100,000 square meter per year line in Hubei; Kasheng Technology has sampled 8-inch pilot material to Nvidia, Intel, JCET, and TongFu. The obstacles are specific: laser drilling throughput, voids when filling high-aspect-ratio vias with copper, and rebuilt handling and fixtures for large panels. Upstream is the sharper constraint, since high-purity electronic glass is held by Corning, SCHOTT, and AGC with more than 90% of global capacity, and a melting furnace takes 12 to 18 months to build.

Consumables That Never Touch the Die: CMP Retainer Rings and PFA Tubing

Not every critical material carries an electrical signal. CMP retainer rings hold the wafer during chemical mechanical polishing. The traditional material is PPS, now being displaced by PEEK for lower wear, longer life, and higher temperature tolerance; China’s market is about 480 million yuan in 2026, growing 12%, with stable growth, decent margins, and long qualification cycles.

Ultra-pure PFA lines, valves, and fittings are the plumbing of wet cleaning, etching, and development. The requirements are extreme: metal ion extraction at the parts-per-trillion level, low particle shedding, and high-purity weldability. Domestic suppliers cover the mid and low end, while semiconductor-grade product still depends on imports from Entegris, Parker, Swagelok, and Nippon Pillar.

The economics of this layer are distinctive. A retainer ring sells for a few thousand yuan, but a 12-inch fab replaces hundreds per year, and once a supplier is qualified it stays unless something goes wrong. This is a slow business and the most cycle-resistant one: it follows capacity, not chip prices.

Five Kinds of Localization Bottleneck

Localization of advanced packaging materials is not one problem but five, and the five do not share a timetable.

The most misread category is the qualification breakthrough type. Specifications look almost there, so people read the gap as imminent replacement. Between sample validation and volume supply sit 18 to 24 months of reliability data and one process re-tune on the customer’s line.

A counter-consensus judgment follows: over the next three years the fastest localizing materials will not be the hardest ones but the ones customers most want to switch. Memory makers are more willing to substitute than logic foundries, because memory is more cost-sensitive and less dependent on the leading node. PSPI, temporary bonding adhesive, and GMC will therefore move faster on the memory chain than on the logic chain.

The Counterintuitive Conclusion: Proof Beats Performance

Lay the six gates side by side and a pattern appears. Heat, moisture, mechanics, electrical, and purity are all questions of whether something can be done. Only the sixth, time, asks whether it can be proven, and for advanced packaging materials the sixth gate is the deepest moat in the industry.

Three short statements follow. First, the repricing of packaging is structural rather than cyclical: when packaging carries a quarter of chip cost, material selection stops being procurement and becomes product definition. Second, the bottleneck is moving from formulation to evidence: most domestic materials can now produce samples that hit the numbers, and what is missing is 18 to 24 months of reliability data, batch consistency records, and one successful process re-tune. Third, the hardest material to replace is not the most expensive but the most embedded: ABF film is hard because it is embedded in substrate process, and PSPI is hard because it is embedded in the customer’s RDL flow.

That is also why the largest capacity and the largest share are two different achievements. The first is bought with investment; the second is bought with time. In this industry time is the only factor of production that cannot be purchased.

What to Do With This in Practice

• Treat interface adhesion and CTE match as first-order requirements, not final checks, because most failures are interfacial.
• Budget 18 to 24 months for any material swap, and lock the reliability plan before the first sample ships.
• Track the memory chain for the fastest substitution progress, since memory customers are the most willing to switch.
• Judge suppliers on process window and batch consistency rather than peak datasheet numbers.
• Evaluate warpage at final package size, not at coupon size, because warpage scales with the square of dimension.
• For fluid handling, specify extractables and particle counts, not just resin purity.
• Treat validated and in volume supply as different states; several 2026 announcements sit in the first category.

Limitations

This article compiles figures from industry trackers, sell-side estimates, and company disclosures as of late 2026, and different houses use different denominators, so market sizes and shares should be read as directional. The underlying research states that seven material families survive the screen without enumerating them, and the grouping used here follows the material classes it discusses. Several company advances sit at sample or validation stage and do not imply volume supply, and vendor-claimed specifications such as 0.1 micron resolution need customer confirmation. Capacity figures are nameplate. Nothing here is investment or purchasing advice; material selection belongs to testing under real process conditions against supplier documentation.

Bottom Line

Advanced packaging materials are not chosen for strength but for repeatability. The 2026 story is that the industry moved from asking whether a material can hit a specification to asking whether anyone can prove it over years, and that question is answered with reliability data and process history rather than datasheets. For the next three years the binding constraints are ABF film supply, high-end PSPI validation, and electronic-grade glass, and the fastest progress will come wherever customers want to switch most.

FAQ

What are advanced packaging materials?

Advanced packaging materials are the polymer films, adhesives, and molding compounds that insulate, bond, and cool chips in 2.5D and 3D packages. Seven families do most of the work: polyimide, epoxy, BT resin, ABF film, PEEK and PPS, fluoropolymers, and silicones or acrylates. They are chosen for repeatability, not peak performance, because every layer must survive three reflow cycles at 260 C.

Why did advanced packaging overtake traditional packaging in 2026?

Advanced packaging crossed half of the global test and assembly market in 2026, about 52 billion US dollars out of 96 billion, or 54%. AI drove it: CoWoS plus test content now carries 21% to 25% of the cost of a high-end compute chip, with gross margins of 48% to 55%. Demand outpaced a near tripling of capacity, leaving TSMC filling only about 80% of orders from big customers.

What is ABF film and why is it in short supply?

ABF film is the build-up insulation layer in high-end IC substrates, a resin found in a monosodium glutamate by-product. Ajinomoto holds 90% to 95% of the market, its next plant starts in 2028 and produces in 2032, and AI packages use 5 to 10 times more film per chip. In August 2026 that supplier cut mainland China allocations by 30%, stretching substrate lead times to 12 to 14 months.

What is the difference between GMC and MUF?

GMC is a granular epoxy molding compound for wafer-level and panel-level compression molding, while MUF is molded underfill that fills gaps and encapsulates the stack in one pass. Both exist because HBM stacks 8 to 12 or more DRAM layers with gaps of only tens of microns, too narrow for traditional pre-molded encapsulation. The more layers a stack has, the more MUF’s single-pass advantage grows.

What is photosensitive polyimide used for?

Photosensitive polyimide, or PSPI, is the dielectric for redistribution layers and TSV insulation in advanced packages. Because it can be exposed and developed directly, it removes the coating, lithography, etch, and strip steps, four operations between layers. Traditional grades cure at 350 to 400 C, so low-temperature grades curing at 200 to 250 C are the entry point for domestic suppliers.

What is the popcorn effect in semiconductor packaging?

The popcorn effect is package delamination during reflow, when absorbed moisture vaporizes and expands a thousandfold. Molding compounds absorb 0.1% to 0.5% water, and at 260 C it becomes steam in seconds and builds pressure until interfaces separate. JEDEC moisture sensitivity levels manage it: MSL 1 parts tolerate unlimited floor exposure, MSL 3 parts need baking after 168 hours.

Why does warpage matter in large AI packages?

Warpage grows with the square of package size, so moving from 50 by 50 mm to beyond 100 by 100 mm turns a manageable deflection into an alignment failure. On a 510 by 515 mm panel, poor CTE control can warp the edge by millimeters and break alignment. Glass cores help: CTE can be tuned to 3 to 5 ppm/C, near silicon’s 2.6, and trials cut warpage by more than half versus organic substrates.

What is the difference between BT resin and a glass substrate?

BT resin is an organic core with moisture uptake of 0.2% to 0.5% and Tg above 200 C, supplying stiffness and flatness in mainstream substrates. A glass substrate trades brittleness for rigidity: CTE can be tuned to 3 to 5 ppm/C against 10 to 17 for organic cores, enabling finer lines and more layers. Glass is in pilot lines with volume expected in 2027 to 2028, while BT remains mainstream today.

Why is underfill needed in flip-chip packages?

An underfill adhesive carries the shear stress that CTE mismatch between die and substrate would otherwise dump onto solder joints. It wicks into the gap by capillary action and cures into a rigid support layer that spreads the load. The formulation has to flow into 50 micron gaps, keep CTE low without becoming brittle, and cure fast without shrinking much.

What is a temporary bonding adhesive used for?

A temporary bonding adhesive holds a thinned wafer on a carrier during backside processing, then releases it intact. It is needed below about 50 microns, and HBM DRAM layers are already ground to 30 to 40 microns, where a wafer behaves like plastic wrap. Release quality decides yield, and laser debonding already held 53.2% of the market in 2025.

Which advanced packaging materials are hardest to replace?

The hardest to replace are the most embedded, not the most expensive: ABF film because it is tied into substrate process, and PSPI because it is bound to a customer’s RDL window. Both sit behind 18 to 24 months of reliability validation and a customer-line process re-tune. Small-market materials such as temporary bonding adhesive can be just as hard, because the barrier is proven history.

How long does it take to qualify a new packaging material?

Plan on 18 to 24 months for a substrate material swap: temperature cycling, biased humidity, drop, and board-level tests. Memory customers typically run 2 to 3 year qualification cycles, and PSPI for advanced packaging is bound to a specific RDL process window. The clock is the sixth gate: samples that hit every number still wait for data, because expensive is survivable and uncertain is not.